Bit Error Test & Arbitrary
Waveform Generation

BERT for Ethernet, OC-768, CEI, InfiniBand and Fiber Channel

SHF’s Bit Pattern Generators (BPG) or Pulse Pattern Generators (PPG), Error Analyzers (EA) and remote heads form a Bit Error Ratio Tester (BERT) suite, which supports a vast number of different applications including high speed Ethernet rates like 100GbE, 200GbE, 400GbE and 1TbE.
The instruments support up to 8 independent channels broadband from < 10 to 64 Gbps. By combining these instruments with our multiplexer (MUX) and demultiplexer (DEMUX) modules, the serial data rate is extended further up to 120 Gbps per channel.
A PAM source is formed by attaching one of our digital-to-analog-converter (DAC) remote heads to the BPG. This way, the fastest commercially available speed on a single serial coaxial interface (128 GBaud / 256 Gbps) is achieved using our PAM-MUX extender head.
SHF’s capability for true PAM4 BER measurements up to a speed of up to 58 GBaud PAM4 (112 Gbps) is also the industries fastest.

Arbitrary Waveform Generation (AWG)

When it comes to signal generation an Arbitrary Waveform Generator (AWG) is the all-in-one device suitable for every purpose in Telecommunication, Optics, Medicine, Radar, Physics or even Quantum Computing.

• Brochure: BERT & DAC for AWG

• Jitter Analysis using SHF 10000 Series BERT Equipment
  A short description of jitter and a tour of the SHF software used for the measurements. Includes an outline of the theory involved.
• DQPSK – Bit Error Test Solution
  Provides a general overview of the optical DQPSK, the generic structure of the SHF DQPSK optical TX and RX modules and the application in conjunction with SHF’s 50 Gbps BERT System
• Skew Control
  This application note describes how the alignment of the output signals from the Pattern Generator SHF 12103A could be adjusted greatly over many bit periods (integer bit delay) and fine-tuned within tenth of a picoseconds (skew control).
• Multi-Level Signal Generation using the Multi-Channel SHF 12103A
  The objective of this note is to provide a simple guide on how to make the best use of the SHF 12103 A Quad-32, 4-channel 32 Gbps BPG, as a multi-bit data source, to realise 4-level electrical signals when used in conjunction with an external broadband power combiner.
• Jitter Injection using the Multi- Channel BPG
  This note presents the setup to allow injection of jitter using a SHF Bit Pattern Generator. It demonstrates that SHF BPG’s are jitter transparent, i.e. it correctly transfer jitter from the clock to the data output signal. This enables jitter tolerance tests as required by many telecommunication standards such as 100G Ethernet and 40 GBit/s OTN.
• Multi-Channel BPG SHF 12103/4 A
  The objective of this note is to provide a reference to illustrate how to make the best use of the truly synchronous features, dual bit rate bands, and multi-channel nature of SHF 12103A and 12104A BPGs. Hardware implementation examples are given towards the realization of many advanced system experiments.

Tutorial Notes

• Tutorial Note 3 – Broadband Communication Signals
  Transmission bandwidth, PRBS signals, correct multiplexing and demultiplexing, eye diagrams, Q-factor, jitter, bit error rate, error analyzers.
• Tutorial Note 4 – Basics of Optical Communication
  Background information about optical detection, polarisation, chirp, dispersion and non-linear effects.
• Tutorial Note 5 – Modulation Schemes
  EA and LiNb modulators, ASK, BPSK and DPSK modulation.

Yes, not all data inputs of the SHF DAC must be used. For example, in case a PAM-4 signal shall be generated only two data input signals must be applied to the DAC. All other inputs can be left floating.

Even operating the DAC as a binary D-type Flip Flop by using one input bit only is possible.

For such cases it is recommended to use the most significant bits of the DAC as these provide the biggest contribution to the output signal amplitude. In other words, the output amplitude is higher if the more significant bits are used and therefore the signal-to-noise ratio will be improved.

As an example, for a 3-Bit DAC, the relation between output voltage U_out and the input data D1, D2 and D3 is calculated as follows:

U_out=D0 · a0 + D1 · a1 + D2 · a2 .

In the data sheet of the SHF DACs you will find a table showing the maximum contribution of each bit similar as below:

The amplitude contribution of each individual input Bit is adjustable by the appropriate slider in the GUI. The minimum voltage contribution an_min is half of the maximum an_max. As the DACs are calibrated, the voltage contribution in Volts is shown in the GUI.

To understand what implications this has on a PAM signal, lets assume the DAC is used in PMA-4 / 2-Bit Mode, i.e. the voltage contribution can be calculated as follows:

U_out=D1 · a1 + D2 · a2 .

For the PAM-4 signal this has the following implications:

• The output amplitude of a 3-Bit DAC in 2-Bit mode (one bit unused) is not as high as with all three bits used.

• If a1 & a2 are reduced by the same factor the overall amplitude gets reduced. By setting all contributions to the minimum the output power is reduced by 6 dB.

• If a1 is reduced (and/or a2 is raised) the inner of the three individual eyes gets bigger. In other words, the symmetry is changed. Please note, the symmetry cannot be changed in case all input bits are used.

• Adjusting all eyes individually (e.g. making the lower eye smaller, while enlarging the upper eyes) is not possible. Such unequal PAM signals can only be realized by programming the input bits accordingly. This would be a feature of a SHF BPG not the DAC itself (please see FAQ below).

The user does not have to worry about setting the individual voltage contributions. The symmetry and the amplitude for PAM-4 can be set in the GUI right away.

DAC GUI

SHF DACs require binary data inputs and a full clock signal.

The term ‘full’ clock means, that the speed of the clock (in Hz) must be the same as the speed of the input data (in bps). For example, to generate a 60 GBaud 8-level signal, one must apply a 60 GHz clock plus three 60 Gbps binary data signals to the DAC inputs.

For proper operation all inputs must be (a) phase aligned and for some applications even (b) bit aligned. A perfect alignment is shown in the graphic below.

(a) Phase Alignment

All SHF DACs are active devices which re-time and re-shape the input signal. This makes the DACs very robust regarding signal impairments and skew at its inputs. Independent from the binary input signal quality one will always receive a perfect PAM signal even if the phase alignment is not as perfect as in the picture above. Nevertheless, the DAC needs to find a valid sampling point and therefore the clock & data input signals must be reasonably good aligned in order to meet the phase margin (hold time) requirements of the device. For example, if an input signal is sampled in its crossing the DAC will produce errors at its outputs.

Proper phase alignment for each single input can be easily verified by operating the DAC in one bit (binary) mode. In case the user has full control of the phase into the DAC (like with a SHF BPG) a perfectly aligned setup can be achieved easily.

(b) Bit Alignment

If above phase alignment requirement is fulfilled the DAC will always produce perfectly shaped PAM signals. For some applications, this is the only requirement one would need to consider.

In case of programming the DAC inputs in order to use it e.g. as an Arbitrary Waveform Generator (AWG) not only the phase alignment has to be considered but also the logical bit alignment. The graphic below shows input D2 is not properly bit aligned and should be shifted by -1 bit.

In case an error analyzer or a scope is used, there are straight forward possibilities to find out whether the bit streams are bit aligned (please be referred to the SHF literature). In addition, with a SHF 12104 A BPG one has full control of the bit alignment. Shifting D2 by -1 bit would be one click in the software and the DAC would have a perfect bit alignment.

Yes, below you will find a simple schematic how this can be done e.g. by utilizing a 4-Bit DAC.

In case a SHF BPG with four outputs is available one can set the bit delay and invert the channel just by a few clicks in the software. No additional hardware is required.

In case an SHF BPG with ‘only’ two channels is available the data bar outputs can be used for D0 and D1. Here, external components have to be used for the one bit delay.

Pre-emphases can be a very powerful tool. In the example below a 30 GBaud PAM-4 signal is transmitted through a 2.5 meter SMA cable.

Input signal without pre-emphases

Output signal without pre-emphases

Input signal with pre-emphases

Output signal with pre-emphases

With this DAC and the SHF 616 A PAM4-Multiplexer we show the generation of various types of high speed (56 GBaud and 112 GBaud) PMA4 signals like PAM with pre-emphasis or PAM with unequal eye openings.

All parts in our current product range of Bit Error Test & Arbitrary Waveform Generation Instruments require the SCC to operate (e.g. the SHF 12106 A BPG). Some obsolete parts of older vintage, however, may require the BCC.

This SHF software is free of charge for the lifetime of your device. The most current version can be downloaded here.

The BCC may be required to operate some older vintage obsolete parts of the Bit Error Test & Arbitrary Waveform Generation Instruments section.

The most current version can be downloaded here.

*Bandwidth depends on the set filter characteristic.