High-Speed Data &
Telecommunication Modules

SHF provides a wide range of high speed modules suitable e.g. for SONET OC-768 / SDHSTM-256, 100 GbE, 400 GbE, 1TbE or Fibre Channel telecommunication systems . The needs of our customers are different; therefore SHF is happy to offer customization to specific applications. A small selection of such assemblies based on our standard product offerings can be found in the customized assemblies subsection.

Raising the speed (up to 120 Gbps serial)
Our multiplexers (MUX) and demultiplexers (DEMUX) offer broadband operation up to 120 Gbps with adjustable amplitude and eye symmetry.

Raising the number of levels (up to 60 GBaud)
Our digital-to-analog converters (DAC) operate at baud rates up to 32 or 60 GBaud. Up to six single-ended serial data streams are converted into one differential multi-level signal. This makes the DAC an ideal electrical signal source e.g. for PAM or QAM applications. Together with one of our our programmable BPGs (Bit Pattern Generators) a high speed “remote head” AWG (Arbitrary Waveform Generator) is formed.

Raising the speed and the number of levels (up to 128 GBaud)
Our PAM4 multiplexer take four binary input data streams, re-time, reshape the signals and multiplex each two to a binary signal of double the speed. Inside the module a two bit DAC converts these two extremely high speed signals to a four level signal.

• Brochure: BERT & DAC for AWG

Yes, not all data inputs of the SHF DAC must be used. For example, in case a PAM-4 signal shall be generated only two data input signals must be applied to the DAC. All other inputs can be left floating.

Even operating the DAC as a binary D-type Flip Flop by using one input bit only is possible.

For such cases it is recommended to use the most significant bits of the DAC as these provide the biggest contribution to the output signal amplitude. In other words, the output amplitude is higher if the more significant bits are used and therefore the signal-to-noise ratio will be improved.

As an example, for a 3-Bit DAC, the relation between output voltage U_out and the input data D1, D2 and D3 is calculated as follows:

U_out=D0 · a0 + D1 · a1 + D2 · a2 .

In the data sheet of the SHF DACs you will find a table showing the maximum contribution of each bit similar as below:

Input D2:
Input D1:
Input Do: on
Output Amplitude: a0_max
Output Amplitude: (example SHF 615 A): 345 mV

Input D2:
Input D1: on
Input Do:
Output Amplitude: a1_max ≈ 2·a0_max
Output Amplitude: (example SHF 615 A): 690 mV

Input D2: on
Input D1:
Input Do:
Output Amplitude: a2_max ≈ 2·a1_max ≈ 4·a0_max
Output Amplitude: (example SHF 615 A): 1380 mV

Input D2: on
Input D1: on
Input Do: on
Output Amplitude: a0_max + a1_max + a2_max
Output Amplitude: (example SHF 615 A): 2415 mv

The amplitude contribution of each individual input Bit is adjustable by the appropriate slider in the GUI. The minimum voltage contribution an_min is half of the maximum an_max. As the DACs are calibrated, the voltage contribution in Volts is shown in the GUI.

To understand what implications this has on a PAM signal, lets assume the DAC is used in PMA-4 / 2-Bit Mode, i.e. the voltage contribution can be calculated as follows:

U_out=D1 · a1 + D2 · a2 .

For the PAM-4 signal this has the following implications:

• The output amplitude of a 3-Bit DAC in 2-Bit mode (one bit unused) is not as high as with all three bits used.

• If a1 & a2 are reduced by the same factor the overall amplitude gets reduced. By setting all contributions to the minimum the output power is reduced by 6 dB.

• If a1 is reduced (and/or a2 is raised) the inner of the three individual eyes gets bigger. In other words, the symmetry is changed. Please note, the symmetry cannot be changed in case all input bits are used.

• Adjusting all eyes individually (e.g. making the lower eye smaller, while enlarging the upper eyes) is not possible. Such unequal PAM signals can only be realized by programming the input bits accordingly. This would be a feature of a SHF BPG not the DAC itself (please see FAQ below).

The user does not have to worry about setting the individual voltage contributions. The symmetry and the amplitude for PAM-4 can be set in the GUI right away.

DAC GUI

SHF DACs require binary data inputs and a full clock signal.

The term ‘full’ clock means, that the speed of the clock (in Hz) must be the same as the speed of the input data (in bps). For example, to generate a 60 GBaud 8-level signal, one must apply a 60 GHz clock plus three 60 Gbps binary data signals to the DAC inputs.

For proper operation all inputs must be (a) phase aligned and for some applications even (b) bit aligned. A perfect alignment is shown in the graphic below.

(a) Phase Alignment

All SHF DACs are active devices which re-time and re-shape the input signal. This makes the DACs very robust regarding signal impairments and skew at its inputs. Independent from the binary input signal quality one will always receive a perfect PAM signal even if the phase alignment is not as perfect as in the picture above. Nevertheless, the DAC needs to find a valid sampling point and therefore the clock & data input signals must be reasonably good aligned in order to meet the phase margin (hold time) requirements of the device. For example, if an input signal is sampled in its crossing the DAC will produce errors at its outputs.

Proper phase alignment for each single input can be easily verified by operating the DAC in one bit (binary) mode. In case the user has full control of the phase into the DAC (like with a SHF BPG) a perfectly aligned setup can be achieved easily.

(b) Bit Alignment

If above phase alignment requirement is fulfilled the DAC will always produce perfectly shaped PAM signals. For some applications, this is the only requirement one would need to consider.

In case of programming the DAC inputs in order to use it e.g. as an Arbitrary Waveform Generator (AWG) not only the phase alignment has to be considered but also the logical bit alignment. The graphic below shows input D2 is not properly bit aligned and should be shifted by -1 bit.

In case an error analyzer or a scope is used, there are straight forward possibilities to find out whether the bit streams are bit aligned (please be referred to the SHF literature). In addition, with a SHF 12104 A BPG one has full control of the bit alignment. Shifting D2 by -1 bit would be one click in the software and the DAC would have a perfect bit alignment.

Yes, below you will find a simple schematic how this can be done e.g. by utilizing a 4-Bit DAC.

In case a SHF BPG with four outputs is available one can set the bit delay and invert the channel just by a few clicks in the software. No additional hardware is required.

In case an SHF BPG with ‘only’ two channels is available the data bar outputs can be used for D0 and D1. Here, external components have to be used for the one bit delay.

Pre-emphases can be a very powerful tool. In the example below a 30 GBaud PAM-4 signal is transmitted through a 2.5 meter SMA cable.

Input signal without pre-emphases

Output signal without pre-emphases

Input signal with pre-emphases

Output signal with pre-emphases

All high-speed modules with a product code starting with a “C” in the product code (SHF Cxxx A/B/C), the SHF 614 B/C and SHF 616 A/B are to be operated by the SCC.

This SHF software is free of charge for the lifetime of your device. The most current version can be downloaded here.

This software package is required to operate all variants of the SHF 611, 612, 613, 615 and the SHF 614 A (later versions of the SHF 614 are to be operated with the SHF Control Center (SCC)).

This SHF software is free of charge for the lifetime of your device. The most current version can be downloaded here.

*Bandwidth depends on the set filter characteristic.